MOS transistor has been developed along the basic principle that “it is possible to realize high speed through miniaturization” according to a scaling rule. However, as the result of progress of excessive miniaturization, it is necessary to increase amount of impurities to be doped in a channel region in order to suppress rapid reduction in the threshold voltage to be caused by miniaturization. Because of “impurity” scattering, mobility of carriers (electrons, holes) transporting from the source to drain reduces greatly. In order to suppress this mobility reduction, various countermeasures have been adopted for forcibly applying “strain” to a silicon atom group constituting the channel.
Electron mobility in an n-channel (N) MOS transistor is improved by applying tensile stress to the channel. Hole mobility in a p-channel (P) MOS transistor is improved by applying compressive stress to the channel.
Japanese Patent Laid-open Publication No. 2003-86708 and its family US 2004/0075148, the whole contents of which are incorporated herein by reference, disclose that in case where the gate length direction is disposed along a <110>direction on an Si (001) surface, NMOS increases an on-current upon application of tensile strain along the gate length direction, and increases an on-current upon application of tensile strain along the gate width direction, whereas PMOS reduces an on-current upon application of tensile strain along the gate length direction (increases an on-current upon application of compressive strain along the gate length direction), and increases an on-current upon application of tensile strain along the gate width direction. These documents further disclose that by forming the contact etch stopper film with a tensile stress film above the NMOS region and forming the contact etch stopper film with a compressive stress film above the PMOS region, the whole characteristics of CMOS can be improved and stress can be adjusted by an area of the contact etch stopper film.
Japanese Patent Laid-open Publication No. 2003-273240 and its family US 2003/0181005, the whole contents of which are incorporated herein by reference, disclose that in the state that the semiconductor surface between the gate electrode and the isolation region is covered with an insulating film functioning as a contact etch stopper, a tensile stress film is formed above the NMOS region and a compressive stress film is formed above the PMOS region.
Japanese Patent Laid-open Publication No. 2006-13322 and its family US 2005/0285137, the whole contents of which are incorporated herein by reference, analyses stresses in various directions and the performances of NMOS and PMOS formed in a silicon substrate comprehensively and proposes to release the stress of a compressive stress film formed on PMOS on the isolation region.
It is also possible to apply stress to a channel by means other than the etch stopper.
When the source/drain regions of an NMOS transistor are made of silicon-carbon (Si—C) mixed crystal (C-doped Si) having a lattice constant smaller than the Si substrate, tensile stress is applied to the Si crystal in the channel region and electron mobility becomes high. Refer to K. Ang et al: IEDM Tech. Dig., 2004, p. 1069, the whole contents of which are incorporated herein by reference.
When the source/drain regions of a PMOS transistor are made of silicon-germanium (Si—Ge) mixed crystal having a lattice constant larger than the Si substrate, compressive stress is applied to the Si crystal in the channel region and hole mobility becomes high. Refer to T. Ghani et al: IEDM Tech. Dig., 2003, p. 978 and Y. S. Kim et al: Proceedings of ESSDERC 2005, p. 305, the whole contents of which are incorporated herein by reference.
By applying stress to the channel of a MOS transistor, it becomes possible to increase carrier mobility and improve the performance of the MOS transistor. Electron mobility in an NMOS transistor is increased by tensile stress, and hole mobility in a PMOS transistor is increased by compressive stress.
It is possible to apply desired stresses to PMOS and NMOS transistors, by etching and digging the source/drain regions of a PMOS transistor and growing Si—Ge crystal and by etching and forming the recess in the source/drain regions of an NMOS transistor and growing Si—C crystal. However, in this case, manufacture processes become complicated. More simpler manufacture processes are desired.
Thus, studies are being made on the structure in which the source/drain regions of a PMOS transistor are etched to form recesses, Si—Ge (or Si—Ge—C) crystal is grown in the recesses to apply compressive stress to the channel, after forming a silicide layer, a nitride film having tensile stress is deposited on the NMOS transistor to apply tensile stress to the channel of a NMOS transistor.
A complementary type semiconductor device may be formed through burying crystal having a larger lattice constant than silicon in the source/drain regions of PMOS, forming a compression stress film on PMOS, and forming a tensile stress film on NMOS. It is desired to improve the performance of the semiconductor device of this type and stabilize the manufacturing processes.